Honored Contributor
Honored ContributorFYI, ring oscillators are pretty difficult in FPGAs, especially if you need to run timing analysis on the loop and/or have tight requirements. Note that the timing models will vary by 2x over PVT, so timing analysis will basically say your oscillator could vary that much too, so it's far from exact. Now, if you just need "a slow clock", building a ring oscillator can be pretty easy if you don't mind it being sloppy, but a more strict implementation is difficult.
The input used by the LUT is determined in the routing process, as this gives significantly more flexibility to the router(and it's just a matter of changing the LUT mask if you change the inputs). Now, this can change timing though as different paths through the LUT can have different delays, but I don't know of a good way to fix them. You could do a routing constriant file(.rcf), but it's not well documented and more for research/university stuff. Check this forum though as I think I've put some stuff up. I also did a ring oscillator design with timing analysis on alterawiki: http://www.alterawiki.com/wiki/ring_oscillator Hopefully that helps, although maybe not with your exact question. My feeling is you put it into a partition, let the router choose what it wants, but when you find one you like lock that partition's placement and routing down.
