--- Quote Start ---
now i change to these codes and the output as shown in picture attachment...
input wire Enable;
input wire [9:0] d_in;
output reg [9:0] max_value;
output reg [2:0] max_location;
reg [2:0] Q;
initial
begin
max_value = 0;
end
always @ (posedge clock)
begin
if (Enable)
begin
if (d_in > max_value)
begin
max_value <= d_in;
max_location <= Q;
end
Q <= Q + 1;
end
end
endmodule
--- Quote End ---
hi GOH WEN SHIN.. i have similar as u..
down votefavorite (
http://stackoverflow.com/questions/37365944/verilog-code-to-find-max-and-min-value-in-an-input?noredirect=1#)
I want to find max and min in input file, read from a memory. This input file size 1000 decimal sample values. I have written the following code to find max and min by comparing with a threshold.
module max_min(input clk, input [15:0]din, output [15:0]dout); reg [15:0]max=0; reg [15:0]min=0; always @(posedge clk) begin if($signed(din)>max) max=din; else if($signed(din)<min) min=din; end assign dout=max;`endmoduleThe problem in above code is that for example the if condition becomes true for (eg) the 2nd cycle sample value, then max will be assigned the 2nd sample value as max sample value. Now let us consider that input din has max sample value at the 15th cycle of all the 1000 samples. So after the 15th cycle max will contain that max value and the output dout will contain max value after 15th cycle and before 15th cycle it will contain the maximum of the first 14 sample values. I want my output i.e max register to contain only the maximum value i.e the 15th value.
plzz help me to sort out this problem..thanks in advance..
-1down votefavorite (
http://stackoverflow.com/questions/37365944/verilog-code-to-find-max-and-min-value-in-an-input?noredirect=1#)
I want to find max and min in input file, read from a memory. This input file containsize 1000 decimal sample values. I have written the following code to find max and min by comparing with a threshold.
module max_min(input clk, input [15:0]din, output [15:0]dout); reg [15:0]max=0; reg [15:0]min=0; always @(posedge clk) begin if($signed(din)>max) max=din; else if($signed(din)<min) min=din; end assign dout=max;`endmoduleThe problem in above code is that for example the if condition becomes true for (eg) the 2nd cycle sample value, then max will be assigned the 2nd sample value as max sample value. Now let us consider that input din has max sample value at the 15th cycle of all the 1000 samples. So after the 15th cycle max will contain that max value and the output dout will contain max value after 15th cycle and before 15th cycle it will contain the maximum of the first 14 sample values. I want my output i.e max register to contain only the maximum value i.e the 15th value.
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