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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to estimate the effective bandwidth of cycloneiv ddr2 HPC II?

Hi all:

I am preparing a cycloneiv+DDR2 based image solution. These is one question puzzles me. What is the effective bandwidth of DDR2 if I select altera's ddr2 HPCII ipcore?

These are 2 channels of image streams, one is 1080p@60hz input and the other is 1080p@60hz output. The pixel clock are both 148Mhz and the data format is RGB888 for each pixel.

So that I need to have a understanding about the DDR2 effective bandwidth when using it as frame buffer. Is any successful project experience that you can share with me? how to decide the DDR2's bit width, driver clock?

tks:)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I'd recommend a conservative value like 80 percent. In practice you should be able to achieve significantly higher than that. Doing out the arithmetic you should quickly find x16 is too narrow and x32 is more than adequate.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Hi

    The project is almost complete. We are using 32bit DDR2 and set the DRR2 HCPII as 160Mhz DDR2 clock output. The input stream is 24bit x 148Mhz and same bandwidth as output stream.

    So these is 8 bits watse on DDR2 side. Then we covert the 24bit RGB to YUV422 as simple compression. We use a 16bit to 32 bits FIFO as cross clock domian FIFO to make the best of DRR2's 32bits. Then it works.

    Is these any solution can make the best of DRR2' s 32bits with 24bits RGB raw input?