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Your teacher is right and i'm full agree with him ;). Unfortunately, this design is a porting of a ASIC one,and i cannot (as much as possible) change anything in it. :mad:
It seems that in ASIC it is possible to align the 2 clocks by using specific constraints onto place/route tools.:rolleyes:
Regards.
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Hi,jj st
yes, in the ASIC world it is much easier to align the clocks as you can do it in an FPGA.
In my point of view you have two problems. First, when you say that CLK1 and CLK3 are unreleated, then you have a so-called clock domain crossing in your design. The Problem is that the position of the clock edges will shift all the time. It is not possible to solve this with constraints. You have to take care for this in your design. If you say that the design comes from an ASIC I'm pretty sure that the design is (hopefully) designed in this way.
When the clocks are related you run into the problem of the so-called clock skew. The clock routing for both clocks will be different. That could cause time violation, e.g Hold time violation in case that the paths between source and destination registers are short.
In case that we are talking only about a few signals and the clock skew is small Quartus should be able to solve the problem , when you use the option :
Settings -> Fitter settings -> Optimize Hold timing -> All paths
Kind regards
GPK
Honored Contributor
