Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- Hello, Some teacher once upon a time said me that is not a good practice of design to use combinatorial nets in the clock inputs. It can cause some problems because the propagation delays. Good luck. Bye. --- Quote End --- Your teacher is right and i'm full agree with him ;). Unfortunately, this design is a porting of a ASIC one,and i cannot (as much as possible) change anything in it. :mad: It seems that in ASIC it is possible to align the 2 clocks by using specific constraints onto place/route tools.:rolleyes: Regards.