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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to equilibrate a Clock Tree with Muxes

I'm facing a problem in my design.:eek: I'm using Quartus 9.0. In my design (coming from ASIC world), i've somes Flip Flops clocked onto a first clock CLK1. I've somes Flip Flops clocked...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hello,

Some teacher once upon a time said me that is not a good practice of design to use combinatorial nets in the clock inputs. It can cause some problems because the propagation delays.

Good luck.

Bye.

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Your teacher is right and i'm full agree with him ;). Unfortunately, this design is a porting of a ASIC one,and i cannot (as much as possible) change anything in it. :mad:

It seems that in ASIC it is possible to align the 2 clocks by using specific constraints onto place/route tools.:rolleyes:

Regards.