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Hi,
maybe I missed somethig. Are CLK3 and CLK1 unreleated ? If, yes and you have paths between the registers in your different clock domains you could not set any constraints
like setup or hold, because the phase of the clock edge is continuous changing. You have to design a real clock domain crossing.
I have a small project attached. Is that like your design ?
Kind regards
GPK
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In my design, CLK3 and CLK1 are unrelated.
Your example is close to mine.
So, how is it possible to align clock edge onto "inst1" and onto "inst/inst7" ? I saw that there is 2 globals. One onto CLK1 and one onto mux_a\out . But the delay of theses global buffers and the delay in the mux is not constrained. So, there is no reason that theses 2 clocks are in phase.
Another way to say it, is "how is it possible to constraint quartus fitter/router to have NO skew between the clock CLK1 that feds inst/inst7 and clock mux_a\out that fed "inst1"?
Regards.
Honored Contributor
