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Altera_Forum
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16 years ago

How to equilibrate a Clock Tree with Muxes

I'm facing a problem in my design.:eek: I'm using Quartus 9.0. In my design (coming from ASIC world), i've somes Flip Flops clocked onto a first clock CLK1. I've somes Flip Flops clocked...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Thanks for the link.

But it seems that my problem is not exactly detailled in this document, or i've missed it.

Could you explain me precisely how to do ?

Thanks a lot.

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Hi,

maybe I missed somethig. Are CLK3 and CLK1 unreleated ? If, yes and you have paths between the registers in your different clock domains you could not set any constraints

like setup or hold, because the phase of the clock edge is continuous changing. You have to design a real clock domain crossing.

I have a small project attached. Is that like your design ?

Kind regards

GPK