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I'm facing a problem in my design.:eek:
I'm using Quartus 9.0.
In my design (coming from ASIC world), i've somes Flip Flops clocked onto a first clock CLK1.
I've somes Flip Flops clocked onto a second clock CLK2.
The CLK2 is in fact a MUXes between CLK1 and another clock, named CLK3.
CLK3 and CLK1 are unrelated, so no problem with them.
I've put a global buffer onto CLK1 and CLK2 (using assigment editor).
But how can i constraint in timequest to align all FFs onto CLK1 "clocktree" (especially those clocked with CLK2) ? I think i've to use -group but how ?:confused:
How can i do the same using classic timing analyser ?
Many Thanks.:)
Regards.
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Hi,
I' pretty sure that you can not use the Classic Timing analyzer. You have to use Timequest. Have a look into the TimeQuest Cookbook:
http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf?gsa_pos=4&wt.oss_r=1&wt.oss=cookbook Kind regards
GPK
Honored Contributor
