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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to enable dual core cortex A9 mode of Cyclone V?

I have used Cyclone V in Single Core configuration but i don't know how can use it in Dual core mode. I have checked the reference manual where i can only see HPS Info Register. This register indic...
Altera_Forum's avatar
Altera_Forum
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12 years ago

The second core does not execute any instruction when the first core send an IPI for task scheduling. Second core is stopped at instruction "S:0xFFFF0100 : LDR sp,[pc,#-164] ; [0xFFFF0064] = 0xFFFFE6A4". So in reality the first core bear all the load. The same code is working fine on i.MX6 on 2 cores. What could be the difference?

P.S.

I am using DS-5.
ALTERA-INSUPPORT22's avatar
ALTERA-INSUPPORT22
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2 years ago

@Altera_Forum Did you find the solution? I am also facing the same situation.

I combined two bin files, core 0 also taking core 1 out of reset, but the problem is core 0 program counter is fine and in range after 0x60000 showing it work fine as in linker its entry point is 0x60000 but core 1 program counter goes to 0xFFFF0004 but its entry point in linker file is 0x100000