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Honored Contributor
Honored ContributorHow to do the timing constrain of the clolks of ALTCLKCTRL
I had instanced a ALTCLKCTRL IP core in my project .The ALTCLKCTRL IP core has two clocks input ports and one output ports, the one is 125MHz(inclk0),the other one is 48MHz(inclk1). So How can I do ...
Altera_ForumHonored Contributor
Honored ContributorWhat you suggested I have done. But the output clock has two different frequencies at the different Time Bucket. In my project ，there are two FIFOs.when the FIFO1 is full ,the rdclk of the FIFO1 changes from 125MHz to 48MHz, meanwhile ,the rdclk of the FIFO2 changes from 48MHz to 125MHz. The wrclk of the two FIFO is always 125MHz.
