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Honored Contributor
Honored ContributorHow to do the timing constrain of the clolks of ALTCLKCTRL
I had instanced a ALTCLKCTRL IP core in my project .The ALTCLKCTRL IP core has two clocks input ports and one output ports, the one is 125MHz(inclk0),the other one is 48MHz(inclk1). So How can I do ...
Altera_ForumHonored Contributor
Honored ContributorUsing TimeQuest. Create a clock for each input clock (inclk0 & inclk1) with their respective frequencies.
Are you concerned this doesn't constrain what you want? Cheers, Alex
