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Altera_Forum
Honored Contributor
14 years agoYou can just create a behavioral description, like the one below.
The tools will then sort it out for you. module LUT4 (input wire A, input wire B, input wire C, input wire D, output wire Z); param INIT=16'b0000_0000_0000_0000; assign Z <= INIT[{D, C, B, A}]; endmodule