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Altera_Forum
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14 years ago

How to define contant look up tables (LUT) ??

Hello..

I can define LUT4 (4 input, 16 bit init value) and LUT5 (5 input, 32 bit init value) look up tables with constant values on Lattice Diamond in this way;

LUT5

# (.init (32'h330FF0CC))

I1 ( .A (x_in[0]), .B (x_in[1]), .C (k_in[0]), .D (k_in[1]), .E (k_in[2]), .Z (f_out) );

LUT4

# (.init (16'h00D8))

I1 ( .A (k_in[0]), .B (k_in[1]), .C (k_in[2]), .D (1'b0), .Z (f_out) );

is there a simple way for this purpose on Altera Quartus (Verilog language, EP3C25E144N fpga CIII) ??

Thanks..

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Quartus has a cycloneiii_lcell_comb primitive for this purpose. See the users guide designing with low-level primitives. But what do you want to achieve?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I want to build hundreds of 32 bit input and 16 bit input look up tables inside the fpga. But they must work very fast and spend minimum logic cells.

    there is also LPM_MUX plugin in the wizard.

    - Is this a simple LUT generator? Are there wasted logic cells on the design output?

    - is it the way for the fastest LUT generation? Or the primitives method output is faster?

    Thanks..
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did you consider to build the look-up tables with internal ROM?

    Generally, I would leave logic cell selection and timing optimization to the design compiler by writing a behavioral description, and timing constraints, if necessary.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You can just create a behavioral description, like the one below.

    The tools will then sort it out for you.

    module LUT4 (input wire A, input wire B, input wire C, input wire D, output wire Z);

    param INIT=16'b0000_0000_0000_0000;

    assign Z <= INIT[{D, C, B, A}];

    endmodule