How to declare an array of registers in CyclonI

Question

Hi,  I am writing a design for an university project (for FPGA CYCLON I, using QUARTUS II software). In this design I want to declare a set (array) of 160 registers of 11bit width each. How can I declare an array of registers so that the synthesis won't decode it into a ram). Then according to write or read signals, I have to implement a writing data from data_in bus to the register which index is set on addr bus if write signal is active and to read data from register to data_out bus if read is active.  What I can think of is just declaring each register separately:   reg     register0;
reg     register1;
.................
reg     register159;  And then creating a huge MUX for write/read operation:  case (addr)
    8'h00 :
        if (write)
            register0 &lt;= data_in;
        else
            if (read)
                data_out &lt;= register0;
    ......
    8'd159 :
        ...............
endcase  But it seems to be not the best way to implement this design. What is the more efficient way? :confused:  Thanks!

altera_forum · Answer

You have some options you can set to prevent Quartus from inferring a RAM. But why don't you want those registers in RAM?

altera_forum · Answer

Because this design will be finally implemented in ASIC and the demand is to have a block of registers.  Can you explain where can I find those options? And if I declare an array of registers, will the following code be synthesizable?  if (write)
    register] &lt;= data_in;
else
    if (read)
        data_out &lt;= register];  Thanks!!

altera_forum · Answer

There is a setting called "AUTO_RAM_RECOGNITION" that you can set to OFF. I've never tried it on one register but you can set it to architectures at least. Probably should work for one register, if not you can just define a register block.

--================================================

-- Set synthesis attribute on architecture

--================================================

attribute altera_attribute : string;

attribute altera_attribute of vhdl_rtl: architecture is "AUTO_RAM_RECOGNITION=OFF";

Best Regards,

Ola Bångdahl

altera_forum · Answer

It's basically synthesizable, assuming suitable register and always block declarations. Generally, these are Verilog syntax rather than Quartus questions.

According to the Quartus Software Handbook, the below Verilog Syntax suppresses RAM inference for my_ram.

reg  my_ram /* synthesis syn_ramstyle = "logic" */;

altera_forum · Answer

--- Quote Start ---

It's basically synthesizable, assuming suitable register and always block declarations. Generally, these are Verilog syntax rather than Quartus questions.

According to the Quartus Software Handbook, the below Verilog Syntax suppresses RAM inference for my_ram.

reg  my_ram /* synthesis syn_ramstyle = "logic" */;

--- Quote End ---

--- Quote Start ---

There is a setting called "AUTO_RAM_RECOGNITION" that you can set to OFF. I've never tried it on one register but you can set it to architectures at least. Probably should work for one register, if not you can just define a register block.

--================================================

-- Set synthesis attribute on architecture

--================================================

attribute altera_attribute : string;

attribute altera_attribute of vhdl_rtl: architecture is "AUTO_RAM_RECOGNITION=OFF";

Best Regards,

Ola Bångdahl

--- Quote End ---

Thank you guys!!!

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How to declare an array of registers in CyclonI

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