Contributor
Frequent ContributorHi there
Are you using the SPI IP from Quartus tools? You can refer to the SPI IP spec in the doc below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf
There are also some design examples available in the link below where you can refer to the connection:
https://fpgacloud.intel.com/devstore/platform/?search=spi&acds_version=any
thanks.
Eng Wei
ContributorThe UG-01085 states:
5.3.1.2. SPI Clock (sclk) Rate
This setting determines the rate of the sclk signal that synchronizes data between
master and slaves. The target clock rate can be specified in units of Hz, kHz or MHz.
The SPI master core uses the Avalon-MM system clock and a clock divisor to generate
sclk.
The actual frequency of sclk may not exactly match the desired target clock rate.
The achievable clock values are:
<Avalon-MM system clock frequency> / [2, 4, 6, 8, ...]
The actual frequency achieved will not be greater than the specified target value.
It looks like the SPI slave has been designed in the normal way and not where the SCLK clock is used to clock the FPGA registers. There does not seem to be an easy way out of this at all.
Frequent ContributorIt is design dependent whether the the clock signal is to connect to the registers. If SCLK is going to clock network, we shall connect it to clock pin.
I am from IO team and might not be the best person to comment on SPI design and usage. If there is any Avalon specific question, I suggest you to file another question and someone will be able to provide support on it.
Thanks.
Eng Wei
Frequent ContributorThis thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
