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patrickk's avatar
patrickk
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5 years ago

How to create an LVDS DDR receiver design in the Stratix 10 with an interface frequency of 480MHz?

I have questions on how to capture source-synchronous DDR (DDIO) data into the Stratix-10 FPGA on the LVDS I/O Banks. We are currently using the 1SX280HU2F50E1VGAS H-Tile device on the Stratix 10 S...
JonWay_C_Intel's avatar
JonWay_C_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi @patrickk

Updating you on my findings.

1) LVDS SERDES IP does not support x2 (DDR), to do so you need to use GPIO IP.

2) The datasheet footnote 66 is suggesting that there could be signal integrity or board skews that could cap the maximum frequency.

3) From (2), even if you have a perfect signal integrity, the maximum frequency you can achieve is 300MHz (as what the Quartus indicated).

4) I tried to check for alternative using the XCVR, but XCVR does not support DDR and XCVR has other limitations with it as well (coupling, run length, etc), which may further complicate things.

patrickk's avatar
patrickk
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5 years ago

Thank you for researching the DDR receiver design for the Stratix 10 FPGA. It is good to know that I need to stay with the GPIO IP and limit DDR transfer speed to 300MHz, best case.

I discussed this with our System Engineer, and he will adjust the system requirements for the lower speed. I will work on the design and see what throughput can be achieved.