How to constrain inter-clock transfers with very low default relationiship (1 ps)?

Hello Richard,

We tested your suggestion to add multicycle path for our project with the current clock tree.

For the data transfer between the clocks 320 and 240 MHz:

- Using setup -start 8 and hold -start 7, we have hold violations.

- The timing violations disappear when we use the same value for setup and hold, for example setup -start 8 and hold -start 8. It also works for the pairs setup/hold 3/3, 4/4, 5/5, 6/6, 7/7.

For the data transfer between the clocks 240 and 280 MHz:

- We have hold violations using setup -start 6 and hold -start 5.

- The timing violations still exist when using the same value for setup and hold.

- The timing violations disappear when we use a value for hold greater than the setup value, for example setup -start 5 and hold -start 6. it also work for the pairs setup/hold 3/4, 4/5.

Does it make sense to use a value for hold equal or greater than the setup value in our case? For me it's clear how the setup work, but I don't understand well the values to use for hold.

Kind regards,

Melissa