How to constrain inter-clock transfers with very low default relationiship (1 ps)?

Sorry for the delay in response. I was busy for the past weeks.

1. For 320-to-240 MHz Transfer, given that the data is stable for 25 ns and the clock enables are asserted once every 25 ns, you can use a set_multicycle_path constraint to tell Timing Analyzer the correct relationship between the source and destination.

Example

set_multicycle_path -from [get_ports {source_ports}] -to [get_ports {destination_ports}] -setup 8 -end

set_multicycle_path -from [get_ports {source_ports}] -to [get_ports {destination_ports}] -hold 7 -end

The setup requirement spans 8 cycles of the 320 MHz clock (25 ns), giving the data sufficient time to stabilize. Similarly, the hold time spans 7 cycles of the 320 MHz clock (21.875 ns), ensuring data remains stable post-capture.

2. Yes, I believe latching the destination register in the middle of the source register's 25 ns window is generally a good strategy because it maximizes the setup and hold times, providing the most timing margin. This means you are latching the data around 12.5 ns from when it becomes valid. Given that 240 MHz has a period of ~4.167 ns, a good phase offset is around 12.5 ns. You might need to select the phase offset such that the clock enable occurs at ~12.5 ns from the start of the data window.

3. My guess is that Quartus may consider the default relationship of 1 ps due to the lack of constraints for the multicycle paths. It seems to indicate an immediate transfer without considering the multicycle nature. Add the set_multicyle_paths so that Quartus understand the actual timing requirements.

P.S. I apologize, but your design is somewhat difficult for me to understand, so I cannot determine which clocks you are referring to.

Regards,

Richard Tan