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MOliv45's avatar
MOliv45
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1 year ago

How to constrain inter-clock transfers with very low default relationiship (1 ps)?

=== SHORT INTRO === Due to some questionable architecture decisions in the past, we ended up with a large circuit implemented in three related clock frequencies using timing division multiplexing. T...
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RichardT_altera's avatar
RichardT_altera
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1 year ago

Please allow me some time to look into this.

Is it okay to share the design so that I can investigate it further?

Is it possible to make any design changes? It seems that it is not possible based on your short intro.

Regards,

Richard Tan

MOliv45's avatar
MOliv45
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1 year ago

Hi Richard,

Yes sure, please find the archived design at https://cernbox.cern.ch/s/scVyb1GatL2mxzr

It is possible to implement changes if they are well justified.

Thanks in advance Richard and have a nice weekend.

Marcos