Honored ContributorQII says that my REFCLKp pin is not connected although clearly it is. I assume it does not like to have a single pin connected via a bus to four CRU inputs on my GXB block?
Will I need to put a PLL between the input pin and GXB CRU clock inputs in order to fan out my reference clock input? This is for a PCIe design. Screenshots attached. Thanks!
Honored ContributorThe issue seems to be how to connect a single input pin to multiple net members. I can't figure out how to do this schematically in the BDF file.
In other words, I want to connect the REFCLKp pin to all rx_cruclk[3..0] member bits. Surely there must be a way to avoid to have to use four pins connected to the same external reference clock signal (especially since using a differential clock)?Honored ContributorOk, I figured this out. The input REFCLKp pin is connected to a bus named 'REFCLKp, REFCLKp, REFCLKp, REFCLKp'. This bus is then connected to the GXB block's rx_cruclk[3..0] input. See attached images.
