How to compare Stratix V vs Xilinx resource

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From that, it seems straightforward to compare FFs where the 5SGXA7 has 939k which compares to the V6LX760 with 948k FFs. How does one compare the 622k Logic Elements for 5SGXA7 to the 758k Logic Cells for V6LX760? Is there an agreed upon convention to convert to logic gates?

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I do'nt think it is easy to convert LUTs to gate figure as this depends on archtitecture of LUT and hence device.

The resource categorisation is identical as shown below, though xilinx reports more useless detailed breakdown:

xilinx slice registers: Altera dedicated registers

xilinx slice LUTs: altera LUTs (aLUTs)

Number used as memory: altera mem aluts

Number of block ram/fifo: altera memory blocks

Number of DSP(48Es): altera dsp elelments...etc