How to close timing with Negative Setup Slack

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Ok, got it. From looking at the timing report it appears there is 9b adder that feeds into a 12b adder, and both are ripple carry implementations.

What you need to do is coerce Quartus to synthesize faster carry lookahead adders that (ideally) use the capabilities of the logic cells in the FPGA.

I found this app note: https://www.altera.com/support/support-resources/design-examples/design-software/vhdl/v_cl_addr.html but it refers to a much older version of the software and an older architecture. However, setting the tool to do more aggressive synthesis/optimization may still work.

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Thanks a lot ak6dn,

Will try this out and be back with the observations..

Jeebu