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Altera_Forum
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9 years ago

How to close timing with Negative Setup Slack

Hi, I am working on a hardware design working at a clock frequency of 200MHz(5 nsec). Setup violation of -0.265 ns is reported by quartus tool. The source clock and the destination clock are sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi ak6dn,

What I meant to say is that, I made a 256 entry ordertable hardware, But during hardware translation, synthesizer would have created some logic(may be for address translation), to add ripple carry adders, as seen from the sta report(I can confirm from the RTL viewer, if you need more clarity).

Attached along is the sta report details for the violation, with actual instance location masked by _instancelocation_

Thanks again.

Jeebu