How to close timing with Negative Setup Slack

Hi ak6dn, Thanks for the quick reply.

So the ripple carry is the result of synthesized hardware, as interpreted by synthesizer. Its a parallel 256 sized combinational logic, which got translated to ripple carry adder, and the critical path includes most of the adders, and hence lead to a negative slack of -0.265 nsec.

The next timing slack is also negative, but negligibly small (~ 5ps).

Regarding cutting down the combo delay with pipelined registers, The main objective of the my low latency hardware is to bring down the latency as far as possible, and hence I m trying to see angles, other than cutting down combo path(Since the negative slack is less than 1ns).

Yes, assuming, I m making the hardware work at ambient conditions at nominal voltages, Can I expect reliable operation ?. Any other suggestions?.

Regards

Jeebu