How to close timing with Negative Setup Slack

Ripple carry over how many bits? If it is small (ie, 8 or less bits) ripple carry is probably the fastest.

However, if it is a 16 bit or more adder a carry lookahead implementation will likely be higher performance.

What is the timing slack on the next 5 or 10 worst case nets? Is it OK, or also in the negative?

If you have a large blob of combinatorial logic that does not meet timing (ie, is greater than the clock interval minus the reg-reg delay) either you have to find a way to reduce the number of logic levels within the logic (shortening the delay) or possibly add internal pipeline registers within the combinatorial logic, such that you now have twice as much time to accomplish the function (of course this assumes externally you can tolerate the additional pipeline clock delay).

If this is just a one-off project than the slack of -265ps is tolerable given you operate at nominal voltage and more or less room temperature.

However, if this is a product that must operate over a wide environmental range (ie, 0'C to 55'C ambient) than you need to do some work.