Honored ContributorHi,
I am using Stratix IV GX board interfaced with an ADC (the sampling rate is 245.76 MHz). I need to add timing constraints to my design. I only have the information on the ADC saying that the Data to clock skew is about -0.3ns minimum and 0.5ns maximum. How can I calculate the input delay for the design? Thank you in advance.
Honored ContributorIn addition to the tCO you got from the ADC datasheet, you need to obtain (or guesstimate) the propagation delay from the ADC to the FPGA (tPD1) and the propagation delay from the clock source to the ADC (tPD2) and from the clock source to the ADC (tPD3).
You can then estimate the input delay as input_delay = tCO + tPD1 + tPD2 - tPD3. You need to obtain a maximum and minimum value for this. I usually use a 6 ps/mm to 8 ps/mm delay for the board traces. To keep me from getting lost, I like to draw a timing diagrams at the various points.
