Forum Discussion

JoelCaruso's avatar
JoelCaruso
Icon for New Contributor rankNew Contributor
5 years ago

How to address two sperate timing constraints in the Arria 10 IO to drive ADC3224 chip (100MSPS)

1st Quartus cannot fit customers timing constrain condition. *as showcased in file* 2nd, Arria 10 cannot fit the timing internally inside FPGA (from DDIO IP output to registers). We checked the prev...