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Altera_Forum's avatar
Altera_Forum
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13 years ago

how to access TSE control port?

Hello all,

I've checked all the possible solutions to get TSE working in gigabit mode, like pll rx and all the suggestion by an440 but no way.

There's another suggestion by accessing a "control port" of TSE

One person suggest, but he didn't explain more about its place, to manipulate with the register called " Extended PHY Specific Control Register " in (offset 20) !!!!!

all the solution keys are posted in the below link, but still not clear to me

http://www.alteraforum.com/forum/showthread.php?t=40423&p=169958&posted=1#post169958

Any one has an idea of how to access TSE register and change register mode?

And please specify the steps from where to start.

Sincerely

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    This register is a PHY register, which is accessible through MDIO. To use the TSE's MDIO master, have a look at the datasheet (http://www.altera.com/literature/ug/ug_ethernet.pdf) at pages 6-2 and 6-5. You will need to write first the PHY's MDIO address in mdio_addr0 or mdio_addr1, and then you can directly read/write the PHY's MDIO registers using the MDIO space 0 or 1.

    In your example, if you write the PHY's MDIO address in the TSE register mdio_addr1 (0x10) then you can access the extended PHY specific control register through the TSE register 0xB4 (which is 0xA0 "MDIO Space 1" + 20)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    hello Daixiwen,

    Thank you for your time,

    I checked this document and I read it before, but as you know there's a lack of steps for beginners in most Altera datasheets.

    I'm struggling to know where to find it, or how to access to these register by which tool. is it by Nios II command shell? is it a file in QII ? is it a *.v or *.c extension file?

    That's what I'm looking for

    https://www.alteraforum.com/forum/attachment.php?attachmentid=7388

    I wish you could support me with a brief steps if you have time.

    I appreciate your help

    Thanks in advance

    Sincerely
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If you are using Nios II, uCOS and the NicheStack, then the Altera drivers will already have configured the PHY's chip MDIO address in the mdio_addr1 register. Then you can directly access the PHY's registers.

    For that you will need to include in your c code the driver file triple_speed_ethernet_regs.h, and from that use the macro IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num) to read a PHY register or IOWR_ALTERA_TSEMAC_MDIO(base, mdio, reg_num, data) to write it. base is the TSE IP base address (as defined in system.h, something like TSE_BASE), mdio is 1, reg_num is the register number (20 in your case) and value the value you want to write.