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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How should I connect clk and pll_refclk0 in RapidIO IP Core of Arria10?

Hi all, In my design I instantiate a RapidIO core and a ATX PLL core, and the device is Arria10. clk is the reference clock for RX CDR block in transceiver, pll_refclk0 is the input clock of ATX P...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago
Hello , I would say connect to the external clock input to the global clock pin and add the clock constraint. Make sure it is connected to the non-inverted (name_p) clock if it is single ended clock input and inverted pin can be left open. Thank you , Regards, Sree