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anm's avatar
anm
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

How reliable is "report_clock_fmax_summary" command?

Hi, I am implementing an OpenRISC processor on a DE0-CV board which features a Cyclone-V FPGA. I am using Quartus Prime v19.1 Standard Edition. In my design I instantiate an Altera PLL in order to ...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi,

    Yes. It is the frequency that the design can reach at this compilation. You may see a different value if you perform a seed sweep or change the compiler settings.

    The value stated in Fmax summary reports potential fmax for every clock in the design, regardless of the user-specified clock periods. The "Note" column reports which analyses restricted fmax.

    Thanks.

    Best regards,

    KhaiY

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Nassos,

No problem. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY