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Altera_Forum
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15 years ago

How quick to go into High-Z?

I am using an FPGA on a parallel bus shared with about 7-8 other devices, mostly ADCs and DACs. I am interfacing the FPGA with the code below to only send data to the Microcontroller when chip-select...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The logic should work, it's generally a good idea to operate the output driver asynchronously. Some delay (several ns) is involved with any FPGA logic of course, I don't expect that it's causing problems at usual bus speeds. If address changes immediately before rd get's active, glitches may occur, but they must not necessarily cause problems. The output drive strength should be adjusted to the bus load and speed requirements.

P.S.: 7-8 devices is quite a lot, it may be a problem of additional capacitive bus load by the FPGA.