Forum Discussion
KSimo1
New Contributor
New ContributorHow much of a cache's cost could be saved by removing the address and data buses?
How much of a cache's cost is taken up in being able to read to it from a bus and write from it to a bus? If that ability were taken away, what would be the cost as a percentage of the original cost?...
ak6dn
Regular Contributor
Regular ContributorThe whole point of a cache memory is to provide very low latency (ie, one clock cycle) random access to a small set of locations. Your architecture does not do that. It appears you are describing something more like a FIFO with a write enable input.
