How long are static timing characteristics valid?

This is a general question regarding Stratix II devices. If I close timing on a design, put it on a board, then leave the board unpowered for 10-20 years, is the timing still guaranteed to be valid when I power the board on? Is there any long term part timing degradation data available or are unpowered parts guaranteed not to degrade?

Thanks,

Steve

I am a long-time FPGA designer, but I have never used Altera devices before. Does Altera provide a better channel for asking this type of question? It seems that all technical questions get sent to the mysupport site, but new users can't ask questions there for 2 days after initial account creation.

Thanks.