Forum Discussion
Sajith_K_Intel
New Contributor
New ContributorHow is an ALM used as Memory cell inside MLAB?
When an ALM inside MLAB is configured as a 32x2 simple dual-port memory, ALM block at least need 5-bit read address, 5-bit write address, write enable, clock, and byte enable. But for an ALUT, only ...
Sajith_K_IntelNew Contributor
New ContributorThis document clearly says "you can configure each ALM in the MLAB as ten 32×2 blocks. The Intel Stratix 10 devices provide one 32×20 simple dual-port SRAM block per MLAB"
The attachment is a view from resource property viewer.
You can see a single ALM placed in MLAB cell, configured as RAM (LUTRAM), and has write address ports, byteenable, write enable, addition to the ALUT inputs used as read address bus. I could not see any documentation detailing about these extra ports. Kindly share if you have some references.
