How i can create a megafunction

Depends on your design entry method. In HDL design entry, definition and instantiation of modules (Verilog) respectively components (VHDL) is a pretty basic language element, so I guess, you're referring to schematic entry.

Here you can also create hierarchical sheets. Draw your intended sub-entitity (the demux logic) save it under a meaningful name and create a symbol for it, either using the default layout or by individually defining the shape. Then you can place instances of this "MegaFunction" in your top schematic or another sub-entity.