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Altera_Forum's avatar
Altera_Forum
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10 years ago

How does one overcome limitation of altera clock control block inputs?

The altera clock control block allows one to switch between 2 PLL clocks. These clock control hard IP blocks are fixed to specific PLLs. Is it bad idea to use normal logic multiplexer only beca...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

thanks,

I shall be possibly translating this code to VHDL for the clock multiplexer. I wonder why this clock multiplexer given in page 16-4 Figure 16-7 does not exist as a megafunction. Anyway, I have a question,

What does the text here mean? This is taken from the clock_mux.v

// A LUT can glitch when multiple inputs slew

// simultaneously (in theory indepently of the function).

// Insert a hard LCELL to prevent the unrelated clocks

// from appearing on the same LUT.

wire [NUM_CLOCKS-1:0] gated_clks /* synthesis keep */;

I do not see any "LCELL" or "Synthesis keep" anywhere in the code apart from these comments.