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AAvil2
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7 years agoThank you so much for your support, both answers was really helpful, i made it work.
kind regards
Alejandro
In Quartus, in the 'Pin Planner' (under Assignments) for your FPGA design, change the 'I/O standard' of the relevant signals to LVDS.
Cheers,
Alex
Thank you so much for your support, both answers was really helpful, i made it work.
kind regards
Alejandro