How do I use the ALTLVDS_RX megafunction with 12-bit

Basically, set up the ALTLVDS megafunction to a 6:1 deserialization factor, then have a 12 bit register which is loaded with the data - in the first clock cycle of the 1/6th clock of the megafunction, load the first nibble (upper if MSB first, lower if LSB first), then in the second cycle load the other nibble. If you use it in external PLL mode, you can then set up the PLL to also generate a half clock (the 1/12th clock) which is has a phase such that it has a rising edge at the falling edge of the 1/6th clock to maximise the setup/hold between the 12bit packing register and the rest of your logic - have an extra 12bit register which is clocked by the 1/12th clock to synchronise it all.