How do I synchronize gray code counts safely across asynchronous clock domains?

Yes I think you are confused.

The pointers cross async clock domain and so a false path is a must otherwise timing will be reported as failed on these paths and will waste closure efforts.

set max delay is a separate issue that you can choose to apply if it helps.

If Xilinx does it automatically in their fifo I hope Altera will follow but I know they put registers close enough anyway by some internal invisible secrets.