How do I synchronize gray code counts safely across asynchronous clock domains?

Sorry for my poor English, I'm from China

I found something strange:in the 《SCFIFO and DCFIFO IP Cores User Guide》，which is the altera megacore fifo user guide，it says that

“

When using the Quartus II TimeQuest timing analyzer with a design that contains a DCFIFO block apply

the following false paths to avoid timing failures in the synchronization registers:

•For paths crossing from the write into the read domain, apply a false path assignment between the

delayed_wrptr_g and rs_dgwp registers:

set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g

[*]}] -to [get_registers

{*dcfifo*rs_dgwp*}]

•For paths crossing from the read into the write domain, apply a false path assignment between the

rdptr_g and ws_dgrp registers:

set_false_path -from [get_registers {*dcfifo*rdptr_g

[*]}] -to [get_registers

{*dcfifo*ws_dgrp*}]

The false path assignments are automatically added through the HDL-embedded Synopsis design

constraint (SDC) commands when you compile your design. The related message is shown under the

TimeQuest timing analyzer report.

Note: The constraints are internally applied but are not written to the Synopsis Design Constraint File

(.sdc). To view the embedded-false path, type report_sdc in the console pane of the TimeQuest

timing analyzer GUI.

”

To my knowledge, the gray code of pointer in the fifo should use the set_max_delay to avoid the ptr delay exceed 1 clk cycle of fastest clk. It should not use the set_false_path constrain to the dcfifo

I don't know why.

When I generate the async fifo in the vivado of xilinx , I can find that the tool generate the set_max_delay constrain in the XDC file.

I was confused