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Altera_Forum
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11 years ago

How do I synchronize gray code counts safely across asynchronous clock domains?

I have a design for a generic asynchronous FIFO that I have used for many years. In this FIFO, I use gray code counters for the read and write pointers to the core memory. These multi-bit pointers mu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Using 3 for setup and 2 for hold still didn't make it pass. However, this time, the fitter only added 5.2ns of delay between the flops.

I may be running into a different problem with the set_max_skew. I am using a single "set_max_skew" constraint that covers all of the synchronizers in this design. This means that the skew will include the wptr sync as well as the rptr sync. Plus, it will include the wptr and rptr for all of the FIFOs, not just a single one. It might work better if I can provide a constraint that is specific for each bus. How would I generically do that?