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Altera_Forum
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11 years ago

How do I synchronize gray code counts safely across asynchronous clock domains?

I have a design for a generic asynchronous FIFO that I have used for many years. In this FIFO, I use gray code counters for the read and write pointers to the core memory. These multi-bit pointers mu...
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Altera_Forum
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11 years ago

Well, that was interesting.

I first tried using a "set_multicycle_path" AND and "set_false_path -hold" with the "set_max_skew". The false_path here, again, caused the set_max_skew to ignore the paths completely.

Next I tried removing the "set_false_path -hold" but keeping the "set_multicycle_path". Now the design misses timing on the max_skew specification. Looking at the worst case path, I see that the fitter has added 13.658ns (!) of routing delay between these 2 flops (which are in the same LAB), presumably in order to meet the hold time requirement between these flops. The best case path (different fifo, different clock, but all lumped together with the single "set_max_skew") only had 8.069ns of routing delay added.

I also tried to use the "-exclude" with set_max_delay, but apparently that is not supported.