Honored Contributor
Honored ContributorThank you for this suggestion kaz.
I have tried this in the past, with no success. The problem with set_max_delay is that the Quartus computation takes into account the clock insertion for both the source and the destination flops, which I don’t care about, and which can yield inaccurate results. So, for this path, the Required time is: + 1.000ns (max_delay) + 2.514ns (pll output through clock tree to receiving flop) – 0.140ns clock uncertainty + 0.228ns Tsu = 3.602ns The Arrival time is: + 3.016ns (input clock pin through clock tree to sending flop) + 0.140ns (flop output) + 3.854ns (chip route) + 0.273ns (cell route) = 7.247ns The slack is 3.602-7.247=-3.645ns. The problem is that I want to exclude the clock tree components from both halves of this computation, so that the slack would be computed only based on the actual chip route from flop-to-flop (3.854ns in this example.) In this particular example, the delta between the 2 clock delays is only 0.5ns. In other parts of the design (or build-to-build variation), the delta can be much larger. It can also have the opposite relationship (clock delay for Required is larger than clock delay for Arrival), meaning that the computed slack is too optimistic. As for using the Altera DC fifo -- I have found that it doesn't work when I compile my design using the tools from a different FPGA vendor :). I like to be able to use this one fifo in a block of shared IP that can be compiled either in Quartus or in a different vendor. Also, it is easy to change the dimensions of my fifo, without having to regenerate using the MegaWizard.
