Forum Discussion
ContributorHow could I understand “IOPLL could drive the lvds tx transmitter in adjacent bank"
Hi,
that sounds plausible:problem is that tx_outclock is generated differently in single-bank and "wide" SERDES. SERDES IP editor doesn't know about final implementation, thus it accpects tx_outclock phaseshifts that are only applicable in single bank design.
A separate pair of PLL outputs drives tx_outclock SERDES channel through dedicated "phase_shifted_tx_outclock_serdes.outclock_tree". In wide SERDES topology, the phase shifted outclock is apparently not available or not used for some reason. You can only implement phase shift values that are aligned with regular bit clock, e.g. 180° for frequency factor 2.
SERDES IP editor should issue a warning about possible phase shift implementation issues.
Super ContributorHi,
can't confirm this problem, bank spanning large SERDES works for me with clock output as well. Check appended test design.
General, clock output can be used to clock the receiver if it isn't able to extract clock from data stream, or the protocol isn't prepared for this option, e.g. not using 8b10b coding with dedicated sync characters.
Related to SERDES IP, clock output isn't but another TX channel sending a fixed pattern.
Regards
Frank
ContributorOh, it's weird.
My quartus is Quartus Prime Version 19.1.0 Build 240 03/26/2019 SJ Pro Edition.
May be there's any Patches which I need to install?
- FvMHI, you previously wrote "Quartus Prime Version 19.1.0.", as we hear now it's Quartus Prime Pro 19.1.0. Unfortunately I don't have older Pro version than 22.4 installed.
- FvMHi,
I found that above posted .qar file generated with Quartus V19.1 Std. can be flawlessly imported in Quartus Pro, your V19.1.0 or any newer version. All you need to do is to regenerate SERDES IP.- lambert_yu
Yes, I just updated the IP and select the enable tx_outclock port.
