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lambert_yu's avatar
lambert_yu
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1 year ago
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How could I understand “IOPLL could drive the lvds tx transmitter in adjacent bank"

Hi, In the "arria 10 Core Fabric and General purpose I/O handbook ": There 's one sentence "For differential transmitters, the PLL can drive the differential transmitter channels in its own I...
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  • FvM's avatar
    FvM
    1 year ago

    Hi,

    that sounds plausible:problem is that tx_outclock is generated differently in single-bank and "wide" SERDES. SERDES IP editor doesn't know about final implementation, thus it accpects tx_outclock phaseshifts that are only applicable in single bank design.

    A separate pair of PLL outputs drives tx_outclock SERDES channel through dedicated "phase_shifted_tx_outclock_serdes.outclock_tree". In wide SERDES topology, the phase shifted outclock is apparently not available or not used for some reason. You can only implement phase shift values that are aligned with regular bit clock, e.g. 180° for frequency factor 2.

    SERDES IP editor should issue a warning about possible phase shift implementation issues.

lambert_yu's avatar
lambert_yu
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1 year ago

Thanks for your strong support again!

I thought I found the different point with your design, you didn't select Enable tx_outclock port under Transmitter Setting. When I set this option in your design, I met the same issue which likes the previous issue.

I want to know the reason for this option, because there's no instructions in guide.

Could you help me?