Forum Discussion
ContributorHow could I understand “IOPLL could drive the lvds tx transmitter in adjacent bank"
Hi,
that sounds plausible:problem is that tx_outclock is generated differently in single-bank and "wide" SERDES. SERDES IP editor doesn't know about final implementation, thus it accpects tx_outclock phaseshifts that are only applicable in single bank design.
A separate pair of PLL outputs drives tx_outclock SERDES channel through dedicated "phase_shifted_tx_outclock_serdes.outclock_tree". In wide SERDES topology, the phase shifted outclock is apparently not available or not used for some reason. You can only implement phase shift values that are aligned with regular bit clock, e.g. 180° for frequency factor 2.
SERDES IP editor should issue a warning about possible phase shift implementation issues.
Super ContributorHi,
please check example design, it uses Bank 2F refclk and TX pins in Bank 2F and 2G.
ContributorHi, FvM
Thanks for your strong support.
By the way, I will need version 22.4 and 25.1 to open it? But I am not have them, would you please to help to provide one under version 19.1?
Best Regards,
Lambert
- FvMAre you using Quartus 19.1 Std. for Arria 10? Didn't expect, never used Arria 10 with Quartus Std. I need to regenerate SERDES IP.
- lambert_yu
We used Quartus Prime Version 19.1.0.
