Forum Discussion
ContributorHow could I understand “IOPLL could drive the lvds tx transmitter in adjacent bank"
Hi,
that sounds plausible:problem is that tx_outclock is generated differently in single-bank and "wide" SERDES. SERDES IP editor doesn't know about final implementation, thus it accpects tx_outclock phaseshifts that are only applicable in single bank design.
A separate pair of PLL outputs drives tx_outclock SERDES channel through dedicated "phase_shifted_tx_outclock_serdes.outclock_tree". In wide SERDES topology, the phase shifted outclock is apparently not available or not used for some reason. You can only implement phase shift values that are aligned with regular bit clock, e.g. 180° for frequency factor 2.
SERDES IP editor should issue a warning about possible phase shift implementation issues.
Super ContributorHi,
error message is incomplete, fitter also reports which signal can't be routed along with Error (175006).
Simple solution would be: Use separate IOPLL in 2F and 2G TX serdes, reference clock can be routed from other bank for TX PLL (but not for RX PLL).
Using the same IOPLL for multiple (adjacent banks) requires implementaion as external PLL, I think. Otherwise no PLL clock is available for routing. This saves an IOPLL resource but requires more clock wiring and involves the possible risk to define an incorrect PLL configuration. Quartus however reports the required external PLL settings when implementing SERDES.
lambert_yuHi, FvM
I presented the detail error message:
(you maybe need to zoom in this page and could see the content clearly) ( because there's image upload policy, I could not provide the original picture)
Simple solution would be: Use separate IOPLL in 2F and 2G TX serdes, reference clock can be routed from other bank for TX PLL (but not for RX PLL).
For this case, I only used the lvds channels in bank 2G, but there's refclk issue and it's not easy to provide other clock source to its refclk pin due to the board design. And it's easy to provide one external clock to the refclk pin of bank 2f.
And I have tried to use the external IOPLL (refclk comes from BANK 2F), I added 1 dummy lvds transmitter in bank 2f which is not the real used and 4 lvds transmitter in bank 2g which are real used. But there's still fitter error.
My fpga is : 10ax115n2f45e1sg
Best Regards,
Lambert
- FvM
Hi,
I tried to trace the problem in Quartus Pro, versions 22.4 and 25.1.
According to my reading of
Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook 2023.01.18, it should be possible to drive SERDES TX IOPLLs in multiple banks from a single refclk pin.
"5.6.6.2.2. Guideline: I/O PLL Reference Clock Source for DPA or Non-DPA Receiver
The reference clock to the I/O PLL for the DPA or non-DPA LVDS receiver must come from the dedicated reference clock pin within the I/O bank.
Note: This requirement is not applicable to LVDS transmitters."But apparently this doesn't work. Without global_clock assignment for the refclk pin, you get routing error described in above posts. With global_clock assignment (which seems appropriate to me), the error turns into well-known Error(18694) "): The reference clock on PLL (...) is not driven by a dedicated reference clock pin from the same bank."
But according to above quoted note, the requirement doesn't apply to SERDES TX PLL.
I'm under the impression that Quartus fitter constraints are not accordance with A10-Handbook specifications and that the requested SERDES TX configuration can't be implemented without using undocumented Quartus settings.
Regarding other option, using a single PLL for adjacent SERDES TX banks, it's not completely clear what "only" in Pragraph 5.6.6.5. Guideline: Pin Placement for Differential Channels means."The I/O bank PLL can drive the differential transmitter channels in an adjacent I/O
bank only in a wide LVDS SERDES Intel FPGA IP transmitter interface that spans multiple I/O banks, where:
• With tx_outclock enabled—the transmitter has more than 22 channels
• With tx_outclock disabled—the transmitter has more than 23 channels"I understand "wide SERDES" as single instance driving pins in multiple adjacent banks. But is it required to use all 22 pins in a bank to advance to next bank? If not, why is the pin count mentioned at all?
- FvMHi,
"wide LVDS SERDES" option seems to solve the problem. Define a single TX SERDES instance with outputs in multiple adjacent banks. IOPLL is generated in the refclk pin bank, LVDS clock tree is propagated to adjacent banks where needed.
