how can I solve this problem

Hi,

use an input clk of 1.024MHz.

Then use a counter:

signal count : unsigned(6 downto 0);

process

begin

wait until clk = '1';

count <= count + 1;

end process;

then

count bit(0) = half clk rate, ignore it

count bit(1) = 1.024MHz * 1/4 = 256KHz

and count bit(6) = 1.024MHz * 1/128 = 8KHz

check jmy math if wrong. Finally make sure you make your clks global(assignment editor)

Or use 10.24MHz and scale accordingly