Forum Discussion
Altera_Forum
Honored Contributor
14 years agonow that i think about it, this still may not work. anyhow...
1. port map the bidir bus to an HDL file that defines the bidir I/O but nothing else 2. run Analysis and Elaboration 3. find the bidir dummy module in the Hiearchy window 4. right click and create a new parition 5. in Assignments > Design Partitions change the Netlist Type for the dummy partition to Empty