Forum Discussion
Altera_Forum
Honored Contributor
14 years agoYes i know...but i am doing a module level synthesis. This module has some huge combo logic and i want to be aware of the timing so that i dont have probs at the top.
Now coming back to interfaces , these wont be in the port list in the top, so i just want to do a module level synthesis as i doubt that this module might cause timing probs when i integrate it. So can you help me as to what i can do regarding this? Thanks :)